In this week IEEE Electronic component and packaging technology conference, Intel It was unveiled that this new chip is developing packaging technology that would allow for large processors for AI.
With the slow increase of the computing needs of AI, manufacturer of advanced GPU and other data centers chips, with the tireless increase of the computing requirements of Moore’s law, is happening to add more silicone sector to their products. But the maximum size of a single silicone chip is fixed at about 800 square millimeters (with an exception), so they have to turn towards advanced packaging technologies that integrate several pieces of silicon in a way that allows them to work like the same chip.
The purpose of three of the three innovations unveiled in the ECTC was aimed at dealing with boundaries as to how much silicon you could squeeze in a single package and how big this package can be. They include the adjacent silicon dies in improvement in technology intellers, a more accurate method for bonding the silicon for the package substrate, and a more accurate way to expand the size of a significant part of the heat removing the heat. Together, technologies enable the integration of more than 10,000 square millimeters of silicon within a package that can be larger than 21,000 mm2-A huge area about the size of a four and a half credit card.
EMIB gets 3D upgrade
How fit the silicone can be in the same package, one of its limitations to do a large number of silicon to do with dying on its sides. Using an organic polymer package substrate to interconnect silicon dice is the most economical option, but a silicon substrate allows you to create more dense connections on these edges.
The solution of Intel was introduced over five years ago, embedding a small slever of silicone in the organic package below the sides of the silicon. Sliver of silicon, called Mib, is etched with fine interconnects that can handle organic substrate, enhancing the density of connections beyond this.
In ECTC, Intel unveiled the latest twist on EMIB technology, called EMIB-t. In addition to the normally fine horizontal interconnects, Emib-t offers relatively thick vertical copper connections called-silicon vias, or TSVs. TSVs allow electricity from the circuit-board below, which allow to connect directly from the long journey to the top of the EMIB directly to the top, instead of reducing the lost power lost from the long journey. Additionally, EMIB-t contains a copper grid that acts as a ground plane to reduce noise in the power distributed due to the process core and other circuits, which suddenly increases its workload.
“It seems simple, but it is a technique that brings a lot of capacity to us,” says Rahul Manapalli, Vice President of Substrate Packaging Technology in Intel. Its and other technologies are described with Intel, a customer can add silicon equal to more than 12 full-sized silicon-10,000 square millimeters of silicon-using 38 or more amib-t bridge in a single package.
Thermal control
Another technology Intel reported in ECTC that helps to increase the size of the package, a low-finish-gradient thermal compression relationship. This is a type of technology used today for the death of silicone for organic substrates. The micrometer-scal bumps of the solder are deployed on the substrate where they will connect to a silicone dye. The dying is then heated and pressed on the microbp, they are melted and connects the interconnects of the package to silicon.
Because silicon and substrates expand at different rates when heated, engineers have to limit the inter-pump distance, or pitch. Additionally, the expansion gap makes it difficult to make very large substrate rich in very large silicon, which is towards going to the AI processor.
Manpalli says that the new Intel Tech Thermal expansion makes mismatch more approximate and manageable. The result is that very large substrates can be populated with dying. Alternatively, the same technique can be used to enhance the density of connections, which is reduced to about one about 25 micrometers.
A flattery summer spreader
These large silicone assemblys will generate more heat than today’s systems. So it is important that the path of heat from silicon is not interrupted. An integrated piece of metal called heat spreader is important for it, but it is difficult to make a large for these large packages. The package may fight the substrate and the metal heat spreader itself cannot remain completely flat; So it cannot touch the top of hot dying, it is sucking with heat. The solution of the Intel was to collect integrated heat spreaders in parts rather than a piece. This allowed it to add additional rigid components between other things to keep it in flat and place.
“Keeping it flat at high temperatures is a major advantage for reliability and yield,” is called Manipalli.
Intel says that technologies are still in the R&D stage and will not comment on that these technologies will start commercially. However, they will be likely to come in the next few years for Intel Foundry to compete with TSMC’s planned packaging expansion.
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